FDMD82100 dual n-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation FDMD82100 rev.c www.fairchildsemi.com 1 november 2013 power 3.3 x 5 d1 d1 d1 s2 s2 g2 g1 g1r d2/s1 d2/s1 d2/s1 d2/s1 1 2 3 4 5 6 11 12 9 10 8 7 pin 1 FDMD82100 dual n-channel power trench ? mosfet 100 v, 7 a, 19 m features ? max r ds(on) = 19 m at v gs = 10 v, i d = 7 a ? max r ds(on) = 33 m at v gs = 6 v, i d = 5.5 a ? ideal for flexible layout in primary side of bridge topology ? termination is lead-free and rohs compliant ? 100% uil tested ? kelvin high side mosfet drive pin-out capability general description this device includes two 100v n-channel mosfets in a dual power (3.3 mm x 5 mm) package. hs source and ls drain internally connected fo r half/full bridge, low source inductance package, low r ds(on) /qg fom silicon. applications ? synchronous buck : primary swit ch of half / full bridge converter for telecom ? motor bridge : primary switch of half / full bridge converter for bldc motor ? mv pol : 48v synchronous buck switch mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous t a = 25 c (note 1a) 7 a -pulsed (note 4) 80 e as single pulse avalanche energy (note 3) 121 mj p d power dissipation t a = 25 c (note 1a) 2.1 w power dissipation t a = 25 c (note 1b) 1 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 60 c/w r ja thermal resistance, junction to ambient (note 1b) 130 device marking device package reel size tape width quantity 82100 FDMD82100 power 3.3 x 5 13 ?? 12 mm 3000 units
FDMD82100 dual n-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation FDMD82100 rev.c www.fairchildsemi.com 2 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 100 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 70 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a23.34v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -9 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 7 a 15 19 m v gs = 6 v, i d = 5.5 a 23 33 v gs = 10 v, i d = 7 a, t j = 125 c 27 35 g fs forward transconductance v dd = 5 v, i d = 7 a 18 s c iss input capacitance v ds = 50 v, v gs = 0 v f = 1 mhz 805 1070 pf c oss output capacitance 176 235 pf c rss reverse transfer capacitance 8 15 pf r g gate resistance 0.1 1.8 3.6 t d(on) turn-on delay time v dd = 50 v, i d = 7 a v gs = 10 v, r gen = 6 9.4 19 ns t r rise time 3.2 10 ns t d(off) turn-off delay time 15 27 ns t f fall time 3.3 10 ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 50 v i d = 7 a 12 17 nc total gate charge v gs = 0 v to 6 v 8 11 nc q gs gate to source charge 3.9 nc q gd gate to drain ?miller? charge 2.7 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 7 a (note 2) 0.8 1.2 v t rr reverse recovery time i f = 7 a, di/dt = 100 a/ s 46 74 ns q rr reverse recovery charge 48 77 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0 %. 3. e as of 121 mj is based on starting t j = 25 o c, l = 3 mh, i as = 9 a, v dd = 100 v, v gs = 10 v. 100% tested at l = 0.1 mh, i as = 30 a. 4. pulse id refers to figure.11 forward bias safe operation area. a. 60 c/w when mounted on a 1 i n 2 pad of 2 oz copper b. 130 c/w when mounted on a minimum pad of 2 oz copper g df ds sf ss g df ds sf ss
FDMD82100 dual n-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation FDMD82100 rev.c www.fairchildsemi.com 3 typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 20 40 60 80 v gs = 7 v v gs = 6 v v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 5 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics f i g u r e 2 . 0 20406080 0 1 2 3 4 v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 7 v v gs = 6 v v gs = 10 v v gs = 5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 i d = 7 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 45678910 0 25 50 75 100 t j = 125 o c i d = 7 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 24681 0 0 20 40 60 80 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMD82100 dual n-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation FDMD82100 rev.c www.fairchildsemi.com 4 figure 7. 0 2 4 6 8 101214 0 2 4 6 8 10 i d = 7 a v dd = 75 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 50 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage f i g u r e 9 . u n c l a m p e d i n d u c t i v e swit ching capability 0.001 0.01 0.1 1 10 100 1 10 50 t j = 100 o c t j = 25 o c t j = 150 o c t av , time in avalanche (ms) i as , avalanche current (a) figure 10. 25 50 75 100 125 150 0 2 4 6 8 v gs = 6 v r t ja = 60 o c/w v gs = 10 v i d , drain current (a) t a , ambient temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs ambient temperature figure 11. 0.1 1 10 100 300 0.005 0.01 0.1 1 10 100 200 10 p s 10 s curve bent to measured data 100 p s 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) single pulse t j = max rated r t ja = 130 o c/w t a = 25 o c this area is limited by r ds(on) f o r w a r d b i a s s a f e operating area figure 12. 10 -5 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 10000 single pulse r t ja = 130 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
FDMD82100 dual n-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation FDMD82100 rev.c www.fairchildsemi.com 5 figure 13. 10 -5 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.0001 0.001 0.01 0.1 1 2 single pulse r t ja = 130 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to- ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
FDMD82100 dual n-channel powertrench ? mosfet ?2013 fairchild semiconductor corporation FDMD82100 rev.c www.fairchildsemi.com 6 dimensional outlin e and pad layout
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